PSX instruction set
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Mirror of [1], with corrections.
Warning: Because psxfin's disassembler uses the wrong order for jalr, the FFH wiki and community uses "jalr rs,rd" instead of the correct "jalr rd,rs".
Instruction Description Syntax Result ----------- ----------- ------ ------ ADD Add Word ADD rd, rs, rt rd = rs + rt ADDI Add Immediate Word ADDI rt, rs, immed rt = rs + immed. ADDIU Add Immediate Unsigned Word ADDIU rt, rs, immed. rt = rs + immed. ADDU Add Unsigned Word ADDU rd, rs, rt rd = rs + rt AND And AND rd, rs, rt rd = rs AND rt ANDI And Immediate ANDI rt, rs, immed. rt = rs AND immed. BEQ Branch on Equal BEQ rs, rt, offset if (rs = rt) branch BGEZ Branch on >= 0 BGEZ rs, offset if (rs > 0) branch BGEZAL Branch >= 0 and Link BGEZAL rs, offset if (rs >= 0) call/ret BGTZ Branch > 0 BGTZ rs, offset if (rs > 0) branch BLEZ Branch <= 0 BLEZ rs, offset if (rs <= 0) branch BLTZ Branch < 0 BLTZ rs, offset if (rs < 0) branch BLTZAL Branch < 0 and Link BLTZAL rs, offset if (rs < 0) call/return BNE Branch != BNE rs, rt, offset if (rs != rt) branch BREAK Breakpoint BREAK breakpoint exception COPz Coprocessor Operation COP(0/1/2/3) function copressor operation DIV Divide Word DIV rs, rt LO = rs / rt | HI = rs % rt 1 DIVU Divide Word Unsigned DIVU rs, rt LO = rs / rt | HI = rs % rt 1 J Jump J address jumps within 256MB JAL Jump and Link JAL address jumps within 256MB, and ret JALR Jump and Link Register JALR rs (rd = 31) jumps within 256MB, and ret 5 ---- JALR rd, rs 5 JR Jump Register JR rs jumps to GPR(rs) LB Load Byte LB rt, off(base) rt = memory[base+off] 8 bit LBU Load Byte Unsigned LBU rt, off(base) rt = memory[base+off] 8 bit LH Load Halfword LH rt, off(base) rt = memory[base+off] 16 bit LHU Load Halfword Unsigned LHU rt, off(base) rt = memory[base+off] 16 bit LUI Load Upper Immediate LUI rt, immed. rt = immed. << 16 LW Load Word LW rt, offset(base)rt = memory[base+off] 32 bit LWCz Load Word to Coprocessor LWC(1/2/3) rt, offs(base) rt = memory[base+off] 32 bit LWL Load Word Left LWL rt, offset(base)rt = memory[base+off] 6 LWR Load Word Right LWR rt, offset(base)rt = memory[base+off] 6 MFHI Move From HI Register MFHI rd rd = HI MFLO Move From LO Register MFLO rd rd = LO MTHI Move To HI Register MTHI rd HI = rd MTLO Move To LO Register MTLO rd LO = rd MULT Multiply Word MULT rs, rt LO = rs * rt | HI = rs * rt 2 MULTU Multiply Unsigned Word MULTU rs, rt LO = rs * rt | HI = rs * rt 2 NOR Not Or NOR rd, rs, rt rd = rs NOR rt OR Or OR rd, rs, rt rd = rs OR rt ORI Or Immediate ORI rd, rs, immed. rd = rs OR immed SB Store Byte SB rt, off(base) memory[base+off] = rt 8 bit SH Store Halfword SH rt, off(base) memory[base+off] = rt 16 bit SLL Shift Word Left Logical SLL rd, rt, sa rd = rt << sa 3 SLLV Shift Word Left Logic Variab SLLV rd, rt, rs rd = rt << rs 3 SLT Set On Less Than SLT rd, rs, rt rd = (rs < rt) SLTI Set On Less Than Immediate SLTI rd, rs, immed. rd = (rs < immed) SLTIU Set On < Immediate Unsigned SLTIU rd, rs, immed. rd = (rs < immed) SLTU Set On Less Than Unsigned SLTU rd, rs, rt rd = (rs < rt) SRA Shift Word Right Arithmetic SRA rd, rt, sa rd = rt >> sa 4 SRAV Shift Word >> Arith Variable SRAV rd, rt, rs rd = rt >> rs 4 SRL Shift Word Right Logical SRL rd, rt, sa rd = rt >> sa 3 SRLV Shift Word Right Logic Variab SRLV rd, rt, rs rd = rt >> rs 3 SUB Subtract Word SUB rd, rs, rt rd = rs - rt SUBU Subtract Unsigned Word SUBU rd, rs, rt rd = rs - rt SW Store Word SW rt, off(base) memory[base+off] = rt 32 bit SWCz Store Word From Coprocessor SWC(1/2/3) rt, off(base) memory[base+off] = rt 32 bit SWL Store Word Left SWL rt, off (base) memory[base+off] = rt 32 bit8 SWR Store Word Right SWR rt, off (base) memory[base+off] = rt 32 bit8 SYSCALL System Call SYSCALL Causes System Call exception XOR Exclusive Or XOR rd, rs, rt rd = rs XOR rt XORI Exclusive Or Immediate XORI rt, rs, immed rt = rs XOR immed Notes: 1. LO holds the integer value of the divide, HI holds the remainder. 2. LO holds the low 32 bits of the multiply, HI holds the high 32 bits of the multiply. 3. On logical shifts, 0s are inserted in the incoming bits. 4. On arithmetic shifts, the sign bit is duplicated in the incoming bits. 5. JALR instructions jumps to GPR(rs), and uses rd to select GPR for return. Defaults to 31. 6. LWL and LWR load parts of a word from unaligned memory 8. SWL and SWR store parts of a word to unaligned memory
